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white paper

Comprehensive S-parameter verification coverage by Analog FastSPICE

Excellence with Analog FastSPICE

Reading time: 10 minutes
In this white paper, we focus on the value of S-parameters in circuit verification and their efficient and accurate processing by the Siemens Analog FastSPICEā„¢ (AFS) engine during analysis. The fundamentals of S-parameters and associated physical properties are explained. The importance of rational fitting and its flow are described, in addition to an alternative flow that does not require fitting. Furthermore, we describe the latest AFS XT advancements in various S-parameter focus areas for enhanced performance,
convergence, memory consumption, feature support, usability and debugging.

Introduction

IC design is transforming at an accelerated pace along with fabrication technology. The need to incorporate more functionality has led to denser dies, multi-die chips, stacked 3D ICs and advanced packaging. Furthermore, design technology continues to progress towards supporting higher data rates to address the increasing demand for more and enhanced connectivity. We now must deal with much more power and ground signals and their distribution. The same goes for clocks and other signals routes on die, between dies, on package and on board. To boost performance in SoCs, frequencies continue to reach new heights for high-speed serial link and memory protocol standards, and so do CPU frequencies. Signal transmission and reflection needs to be well understood to properly design for signal integrity in various signal conduits. Furthermore, custom passive structures such as inductors, T-coils, capacitors, and resistors are being innovated in each technology progression to meet design challenges and specifications related to frequency synthesis, noise filtering and bandwidth extension. S-parameters (scattering parameters) play a crucial part in IC design, and in this paper, we focus on their importance for accurate design considerations and how AFS simulation technology can broaden your IC design verification scope.

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