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Comprehensive layout reliability verification for memory design

Diagram of a common centroid check applied to a row of layout devices of styles A, B and C that should all have a common center, showing the A devices do not comply.
Memory chips are used for storage in low-power applications due to the read/write speed of RAM. Accurate, consistent memory performance is essential to these applications. Ensuring the reliability of NAND, DRAM, and other memory structures requires comprehensive reliability verification for both front-end and back-end memory designs. The Calibre® PERC™ packaged checks flow enables designers to quickly and easily select, configure, and combine pre-coded reliability checks to validate circuit layouts and highlight issues that may impact memory performance or result in operational failures.

Calibre PERC packaged checks simplify reliability verification for memory design layouts

With increasing memory design complexity, accurate and full reliability verification coverage of multiple effects and design requirements is essential. With the Calibre PERC packaged checks flow, designers can select, configure, and combine pre-coded reliability checks to detect issues that may impact memory performance or result in operational failures. Because designers can use the Calibre PERC packaged checks flow without the limitations of check coding or complex setup, running reliability verification on memory designs is easier, faster, and more consistent.

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