Comparing multi-patterning at 5nm: SADP, SAQP, and SALELE
Siemens EDA and IMEC collaborate to analyze and optimize self-aligned multi-patterning foundry processes and IC design layout decomposition and verification solutions
Although the use of self-aligned multi-patterning techniques, such as self-aligned double and quadruple patterning (SADP, SAQP) and self-aligned litho-etch litho-etch (SALELE), is becoming increasingly popular in advanced IC design process nodes, the specifics of each technique have unique advantages and disadvantages. The optimal solution must take into account the process and design benefits and limitations that affect issues such as track flexibility, block mask limitations, edge placement errors, pitch walking, parasitic capacitance, and EUV lithography. Siemens EDA collaborated with IMEC to identify and characterize self-aligned multi-patterning process sensitivities and constraints with the goal of identifying both foundry process improvements and better IC design layout decomposition and verification solutions to mitigate pre-tapeout issues and improve manufacturing yield for multi-patterned IC designs.