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White Paper

CMP simulation solves manufacturing errors before they actually exist

Effective planarization during chemical-mechanical polishing (CMP) strongly depends on the integrated circuit (IC) layout design—in particular, on the pattern density and other geometric characteristics. As part of a design-technology co-optimization (DTCO) flow, modeling and simulation of post-CMP surface profiles should be performed prior to actual manufacturing. SK Hynix and Siemens EDA teamed up to demonstrate how CMP modeling and simulation in a DTCO flow can accurately predict device damage caused by dishing and thickness variation. Improving designs before manufacturing saves both design companies and foundries the time and cost of manufacturing failures.

Accurate CMP models and process simulation are critical elements of a successful IC DTCO process

Post-CMP surface profiles are represented in simulation by topology changes, which are caused by the thickness difference between patterns with different geometry characteristics, such as pattern density, perimeter, etc. Fixing planarization failures or hotspots to eliminate device damage during the CMP process is more effective when done during the design process. Because many CMP hotspots are due to design-specific layout issues, they can often be corrected before sending a design to manufacturing.

SK Hynix and Siemens EDA collaborated on a project to test how well CMP modeling and simulation can predict damage caused by the CMP process. They built a CMP model using the Calibre CMP ModelBuilder tool and tested it on multiple test chip patterns. The results show that CMP modeling can successfully predict device damage by accurately simulating dishing and thickness variation induced by the CMP process. Foundries can use this information to provide design companies with suggested optimizations to strengthen IC designs against erosion and dishing defects.