white paper

Catapult for a Power Optimized ESL Hardware Realization Flow

Catapult for a Power Optimized ESL Hardware Realization Flow

This paper describes, in general, the Catapult® flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult Low-Power design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low-power optimizations turned on. With low-power optimizations on, Catapult uses Siemens EDA's PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

Share

Related resources

A hardware-centric approach to checking HLS code before synthesis
Blog Post

A hardware-centric approach to checking HLS code before synthesis

Excerpt from article: “A hardware-centric approach to checking HLS code before synthesis“ Finding coding problems in C++ or SystemC code…

Closing the Gap in Software Skills for Verification Engineers
Blog Post

Closing the Gap in Software Skills for Verification Engineers

I'm excited to announce next month's U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification…

SLEC System Factsheet
Fact Sheet

SLEC System Factsheet

SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models