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Building CMP models for CMP simulation and hotspot detection

Screenshot displaying visualization of results from CMP simulation and hotspot detection applied to IC design layout
CMP is used to improve the planarity for both FEOL layers like shallow trench isolation STI, and BEOL layers like metal interconnect. Pre-manufacturing detection and correction of CMP hotspots through the use of CMP modeling has become an essential step for many process engineers and designers. The CMP model must not only simulate post-polishing results for multiple materials due to the patterns’ geometry specifics, but also capture long-range polishing effects specific to a given CMP process.

CMP simulations enable designers to optimize IC design layouts before manufacturing

CMP modeling has become a powerful tool for both process engineers and chip designers. It enables design teams to detect potential CMP hotspots prior to manufacturing by providing visualization and analysis of simulated CMP results. The Calibre CMP ModelBuilder and Calibre CMPAnalyzer tools from Siemens EDA support CMP model building, multi-layer full-chip CMP simulation, and hotspot detection and analysis. Efficient, accurate CMP simulation is crucial to continuing design process optimization while improving manufacturing results.

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