Bringing reset and power domains together

The Unified Power format (UPF) standard enables designers to add power intent for a design. For power management, designers typically partition a design into power domains. Interactions between these power domains are done through various power control logic, like retention logic, isolation logic, and level shifters. Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design.

This paper examines issues in reset domain crossings introduced by UPF instrumentation and describes enhancing a static verification tool with new rulesets.

An Efficient Methodology for Power Aware RDC

This paper explains how metastability can be introduced by UPF instrumentation into the reset domain crossing space, describes the challenges designers encounter while working with power-aware RDC analysis, and investigates how newly introduced resets due to UPF instrumentation can affect the data interactions between reset domain paths crossing various power domains. We depict issues in various valid scenarios from a real life SoC and show how low power UPF strategies, like the insertion of isolation cells, can have a huge impact on the reset strategy, as the number of new resets increase dramatically. These issues if undetected, may result in a higher verification turnaround time and unnecessary ECOs, resulting in costly respins.

The conventional RDC methodology still holds good for power aware designs but there is a need to refine the methodology to incorporate certain issues which may creep in due to power instrumentation. We suggest a few RDC checks which are otherwise missing in static verification
tools. These checks ensure the correct propagation of resets and reset connectivity to the blocks which are in an on/off power state. We share an efficient methodology to deal with these new power-related RDC issues.