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Better layouts in less time: AMD and the Calibre RealTime Custom interface at 20nm and below

Better layouts in less time: AMD and the Calibre RealTime Custom interface at 20nm and below
AMD achieved significant productivity improvement on a custom 20nm memory IC design by using the Calibre RealTime Custom interface to fix design rule checking (DRC) errors in the design environment. The Calibre RealTime Custom interface not only provided immediate DRC feedback, enabling a rapid trial-and-error debugging process, but also helped designers learn the new 20nm DRC rules as they iterated to find the optimum resolution for each DRC violation. As a result, the Calibre RealTime Custom interface allowed the AMD designers to improve the quality of the layout because they were able to concentrate on optimizing the design.

In-design, on-demand signoff design rule checking for analog, mixed-signal, and custom IC designs

The Calibre RealTime Custom interface provides designers with one tool and one interface, accessible as an integral part of the design cockpit, throughout the IC design and verification flow. With its ability to perform all checks that can be run with the Calibre nmDRC platform, including recommended rules, pattern matching, equation-based DRC, and multi-patterning, the Calibre RealTime Custom interface lets custom, analog, and mixed-signal IC designers correct and adjust their designs during the layout process to produce a design that is DRC-clean, resistant to manufacturing variability issues, and optimized for the most desirable performance and operational characteristics. Designers get immediate feedback as they edit the layout, ensuring DRC-clean, optimized custom designs in the shortest time possible. It also ensures Calibre sign-off confidence by using the same foundry-qualified rule decks and DRC engine used by the batch Calibre signoff process.

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