Automated post-processing of DRC errors improves debugging productivity

Automated post-processing debugging flows enable designers to more quickly and accurately analyze and fix (or waive) a wide range of complex error conditions in design rule checking (DRC) and design for manufacturing (DFM) verification. By providing designers with more precise and detailed information about a wide variety of DRC/DFM errors, automated analysis and processing of errors, and visual displays of error distributions, the advanced post-processing functionality not only helps design teams move rapidly through debugging flows, saving valuable time and resources but also improve design quality.

Quickly and accurately find, analyze, fix, or waive complex IC design error conditions in DRC/DRM debug with automated post-processing

By enhancing and expanding Calibre Auto-Waivers post-processing functionality beyond just DRC/DFM error waiving, Siemens EDA enables enhanced IC design debugging strategies that provide designers with additional data that improves and speeds up many debugging processes, including antenna violations, curve errors in silicon photonics designs, constraint variants, and error distribution analysis. Debug hints that help designers zero in on root cause, post-verification processing of DRC results that inserts additional properties to facilitate debugging flows, automatic adjustment of waiver tolerances—these types of capabilities add value and improve productivity across the entire DRC/DFM debugging flow.