Automated compliance analysis of serial links reduces schedule risk

The problem: lengthy prototype debugging

Most high-speed serial links don’t get verified once routing is complete because the process is time consuming and skill-intensive – and SI experts are in short supply. As a result, most serial channels are laid out according to rules, verified through manual inspection and released to fabrication without thorough analysis. Unverified channels can result in lengthy (and hectic) prototype debugging, board spins and schedule slips. Until now, there has been no other choice.

The solution: automated post-route verification

This paper discusses an automated post-route verification process with HyperLynx that can verify all the channels in a design for detailed compliance with a SerDes protocol standard – automatically, overnight. This allows designers to find problems early in the layout process when they’re easier to correct, and release designs for fabrication with confidence, knowing all their serial channels have been verified.

Learn more about serial link analysis.