Low power challenges in place-and-route
Performance, power, and area (“PPA” for short) is a phrase the IC design community uses when describing the three key areas to focus on in optimizing an IC design. Traditionally, performance has been the primary focus, but as designs have moved to smaller, more advanced process nodes, and switching activity has become a dominant component in power consumption, power is often the dominant focus in PPA.
How can strict power targets be achieved without sacrificing performance during the implementation phase of the IC design process? Many challenges of achieving low-power during place-and-route relate to how well the place-and-route software handles multiple power domains and the kinds of optimizations the software performs throughout the flow to achieve low power goals.
The Aprisa place-and-route tool low-power solution
The place-and-route software used in the digital implementation flow must be able to buffer on multiple power domains without errors and perform placement of all power management cells such as level shifters, isolation cells, power switch cells, and retention flip-flops. Power-sensitive designs also require routing secondary power/ground pins and routing to the power grid inside the voltage islands.
This white paper examines the Siemens Aprisa place-and-route software low-power capabilities, including:
PowerFirst implementation technology that reduces total power consumption
Support of multi-power domain methodology