Applying machine learning methods to accelerate advanced process node yield ramp
New methods to identify, root-cause, categorize known yield detractors, and flag unknown potential new risk patterns help designers mitigate product yield risk and benefit from continuous learning. Accumulated learning from each new product drives improved testing vehicles, better process optimization, and enhanced PDKs, all leading to more robust designs with higher performance and improved yield. In this paper, we describe innovative machine learning methods in design for manufacturing (DFM) and design technology co-optimization (DTCO) applications to improve process, design enablement, and process yield ramp.
Benefits of machine learning for IC manufacturing
As the IC industry marches forward to continuously more advance technology nodes, manufacturing complexity and product yield ramp grows ever more challenging. The semiconductor industry constantly searches for innovative methods to guarantee high-quality and high-yield products. We introduce a new method to analyze and mitigate new product risk.
Leveraging machine learning and big data technology, we identify high risk patterns, build a database of accumulated learning, prioritize failure inspection and feed data back to perform process optimization, improve DFM and DRC rule decks, and ensure a rapid yield ramp for current and future products. We call this machine learning-enabled closed loop DFM.
Machine learning-enabled closed loop DFM contains four major components. Synthetic layout generation enables early pattern learning, providing layouts to analyze before the first real design is available. LFD lithographic hotspot detection evaluates pattern and process interaction to reveal manufacturing weaknesses. SONR design analysis captures layout signatures and analyze them against an accumulated database of known patterns. Our big data Calibre MLDB database provides storage and query on pattern signatures and their properties.