Analog mixed-signal verification methodology for high resolution high frame rate CMOS image sensor SoCs

Complementary CMOS image sensors are a major driver in lucrative digital imagery markets. Used in today’s digital cameras and mobile phones, CMOS image sensors (CIS) have strict high-resolution and high-frame rate requirements. As a result, design verification of CIS is a major challenge. This white paper details how a leading global manufacturer of electronic instruments and electromechanical devices adopted Siemens EDA’s Analog FastSPICE™ (AFS) platform with AFS eXTreme technology and Symphony mixed signal platform to realize over a 3X speed improvement compared to competitive solutions while maintaining required accuracy.

Ametek verification methodology

The verification for CMOS image sensors can be broken down in three stages. Firstly, at the pixel level, the interest is in characterizing performance in terms of device noise, dynamic range, linearity, etc. The second stage of verification consists of the analog readout signal chain consisting of the column
circuitry. At this stage, designers individually characterize the performance of each of the sub-blocks like VLN, S/H, ADC and SRAM both at the schematic level and post-
layout extracted level. For the first two stages of verification, Ametek adopted Siemens EDA’s Analog FastSPICE (AFS) platform with AFS eXTreme technology to achieve the desired accuracy at significant speed up compared to competitive
simulators.

In the third and final stage, for full-chip functional verification of different modes, Ametek deployed Symphony, Siemens EDA’s next-generation mixed-signal platform. Symphony is the industry’s fastest and most configurable mixed-signal solution that accurately verifies design functionality, connectivity, and performance across analog/ digital interfaces at all levels of the design hierarchy.