The growing market for silicon photonic integrated circuits has led to the need for reliable, automated physical and manufacturing verification process flows that address the unique physical characteristics of silicon photonics designs. Fortunately, EDA companies have recognized that there is no need to invent new tools, or even reinvent the tools and processes already in place for electronics verification.
By expanding and adapting the use of established physical verification and optimization functionality, like equation-based DRC, automated waiver processing, and smart fill optimization, EDA companies have enabled their tools to accommodate the new components and design concepts of silicon photonics designs and provided photonics designers with an automated and standardized path to tapeout.