A novel simulation flow for DDR5 systems with clocked receivers
In this paper
This paper begins with an overview of the DDR5 specification, forwarded-clock architectures, and equalization techniques. The unique aspects of DDR5 IBIS-AMI models and the resulting impacts to the simulation methodology are explored. A novel EDA tool simulation flow for capturing both the non-LTI effects in the DDR5 system and the low BER required in the DDR5 specification is presented. Clocked IBIS-AMI receiver models are then introduced into the simulation flow, and the resulting impact to jitter and crosstalk are presented. Finally, future challenges for simulating DDR5 systems are discussed. Contents
Introduction
DDR5 JEDEC specification from a simulation perspective
DDR5 device models
Novel clocked simulation flow
A custom advanced IBIS-AMI flow Conclusion