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A novel approach for HW/SW co-verification: Leveraging PSS to orchestrate UVM and C tests

black latex gloved fingers inserting a chip into a chassis

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verification by driving UVM and C tests and controlling the interaction between them.

Orchestrating the execution of HW/SW co-verification

HW/SW co-verification is becoming incredibly challenging. A way to cross the boundaries between UVM-based tests and C-tests in an organized and seamless way is called for. PSS is the best language and methodology to orchestrate the execution of HW/SW co-verification, by defining the actions’ abstract scenario, which can be solved in a random fashion. This PSS model manages the design configurations, attributes, resources, and memory management. Also, it defines a realization model which can drive synchronization of UVM-based tests and C-tests.

This paper discusses some of the building blocks used to help achieve seamless HW/SW co-verification integration and a few case studies using our new methodology, which can be summarized in the following steps:

1. Explore testbench environment and develop PSS model

2. Debug PSS (abstract and solved) models using Siemens’ PSS-compliant user interface debugger tool

3. Implement the realization model by adding the contents of the actions’ exec blocks for both C and UVM tests

4. Solve PSS module and generate corresponding tests (C and UVM) using Siemens’ PSS-compliant tool

5. Integrate generated UVM/C tests into UVM test bench using SV interfaces and DPI-C

6. Compile and simulate the TB (running tests on target platforms)

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