The power of SSN

Joe Reynick, Technology Enablement Engineer at Siemens EDA, explains why Tessent's packetized test solution, Streaming Scan Network, offers an inherent power advantage over traditional DFT architectures. He reviews IR drop and ground bounce, how to mitigate IR drop for silicon bring-up, qualification, and production test, why SSN helps, how Iddq is used today, and Tessent's hierarchical SSN and ATPG approach to Iddq test.

ATPG power trends

Large designs with high scan power have increased yield loss due to IR drop. Most scanned logic is in abutted blocks or cores. Iddq testing is widely used but is used in different ways than in the past. These trends lead to two key challenges regarding power during IC test: how to improve scan-based IR drop and how to support hierarchical Iddq.