Tessent MemoryBIST shared bus learning

A presentation from Harshitha Kodali, Product Engineer at Siemens EDA, gives a technical overview of the Tessent MemoryBIST shared bus learning. Shared bus learning maps the physical memory composition of each logical memory and validates the cluster and logical memory library files.

Shared bus interfaces and memory test

These days, designs contain a huge number of memory arrays embedded in the core, and these memories often consume a substantial portion of the total chip area. This increase in memory size and number implies extra hardware cost for the associated memory built-in self-test (MBIST) logic. In addition to the area of the MBIST logic, there may be additional costs due to increased routing. It may even negatively impact the chip's performance in the critical functional paths to and from memories.

A shared bus architecture provides a common access point for several memories, allowing users to optimize routing and core performance. In addition, a shared bus architecture provides flexibility to users to route design-for-test (DFT) signals along functional paths behind the shared bus interface. Tessent MemoryBIST instruments automatically connect to the DFT signals to apply MBIST patterns through the shared bus interface.

What is shared bus learning?

Tessent MemoryBIST provides an automated approach called shared bus learning to map the physical memory composition of each logical memory and validate the cluster and logical memory library files. It is recommended to run shared bus learning on a single, stand-alone cluster before DFT insertion. Shared bus learning involves physical-to-logical mapping automation and library validation. Watch the video to learn more.