STMicroelectronics: Advanced high-sigma standard cell yield verification methodology using AI-powered Solido Library Verifier

STMicroelectronics is a global leader in various sectors, such as automotive, industrial, and consumer electronics. It is renowned for high-quality designs that power a diverse range of applications with stringent functional requirements. To optimize for power, performance and area (PPA) across their extensive product portfolio, designers are increasingly utilizing a broader operational range of library IP in their designs. However, each process technology has its own variability effects on these IPs due to manufacturing variations, which when combined with the sheer number of library cells, make traditional yield verification methodologies prohibitively expensive. Consequently, a high-throughput verification methodology for Process Design Kit (PDK) development has become critical.

At ST, we introduced a transformative method using the SolidoTM Library Verifier, that is optimized for batch verification of library IP. This solution is driven by an in-simulator AI engine, performing High-Sigma yield verification with SPICE accuracy. By employing this next generation yield solver, SPICE simulator and Additive AI technology, STMicroelectronics achieved expedited design verification across hundreds of corners with 7x-12x speedups, resulting in many months' worth of time savings.