SSN and deterministic on-chip compare

Joe Reynick, Technology Enablement Engineer at Siemens EDA, describes deterministic on-chip compare with the Streaming Scan Network. The presentation covers SSN ATPG responses, recommended test patterns and on-chip compare.

SSN for on-chip compare, diagnosis, and bring-up

The SSN architecture presents benefits beyond simplifying DFT implementation and saving test time. It allows for efficient on-chip compare of of identical modules and non-identical modules. He describes the use mode that streams data in through the SSN, does on-chip compare with stick-bit responses for each block, and streams out through the IJTAG network.

SSN is useful in silicon bring-up and debug. Reynick describes how to verify the SSN path with a continuity pattern that bypasses the SSH (Streaming Scan Host) and how to verify the SSH with a loopback pattern. He also covers the recommended SSN patterns to use for first silicon test and for production test. Reynick describes how to prepare the database for layout-aware diagnosis and how to diagnose block-level failures on the tester.

Renick comes back to on-chip compare, giving more detailed descriptions and examples of optimizing test for identical cores.