Simplified physical verification of 3D ICs through​ 3Dblox

In the domain of 3D IC physical and circuit verification, the biggest hurdle has been the challenge arising from the simple fact that users can make independent choices of chiplet and processes to include into a 3D IC design. This freedom of choice makes it all but impossible to have a traditional verification deck that can run on any 3D IC design, since only the designer knows what is in that design. Siemens EDA Xpedition™ Substrate Integrator and Calibre® 3DSTACK tools have been providing a heterogeneous package assembly verification flow for several years now, and are proven in multiple production environments. With the availability of the TSMC 3Dblox standard language, and our long-history of collaboration with TSMC, we were able to quickly embrace the benefits to enable the development of heterogenous assembly design kits (APDKs). With standardized data, physical verification of a 3D IC design can now be largely automated, providing Calibre accuracy while remaining fully independent of the design flow or design tools used.