Silicon Photonics to Integrate Chiplets

Heterogeneous Chiplet integration in harsh environments is a technological challenge that involves working on physical limits for the design of IC substrates/interposers incorporating alternative first-level interconnect technologies. Chiplet manufacturing packaging compliance requires new approaches to the system architecture and system design of multifunctional SoP, including the micro integration of silicon photonics D2D connections, new first level assembly technologies of flip chip DIE's, heat sinks and mold materials to manage thermal hotspots.