Silicon lifecycle redefines design for test

A growing number of safety-critical and mission-critical applications require extremely reliable operation. In automotive applications and large-scale data centers, we rely on design-for-test (DFT) not only for manufacturing but throughout the entire silicon lifecycle. At more advanced technology nodes, especially those at 7 nm and below, and with advanced packaging like 2.5D/3D multi-die packaging, we observe new and more complex parametric defects and reliability risks related to aging. Several companies reported Silent Data Corruption Errors in large-scale data centers. A closer examination of the problem shows four underlying issues: test escapes, early life failure, random/latent/aging defects, and environmental conditions that lead to malfunctions.

In this Keynote presentation delivered at ETS 2023, Janusz Rajski, Vice President of Engineering, Tessent, reviews the challenges posed by these issues and examines the feasibility of emerging solutions to address them.

Traditionally, we use deterministic structural tests to achieve high-quality in-chip manufacturing and rely on logic BIST for in-system tests. But the test quality achieved by logic BIST is insufficient. Can a deterministic structural test, periodically applied during in-system, achieve the required high reliability? How can the test quality be improved to reduce test escapes in manufacturing? Can stress tests be refined to reduce early mortality? Can environmental monitoring detect load conditions or aging leading to errors and prevent them from manifesting themselves?