Samsung Foundry insights on full chip Calibre PERC checks development, optimization and automation

Samsung Foundry is a leading provider of advanced process technology for integrated circuit (IC) design manufacturing. Full chip verification for compliance with foundry ESD rules is a critical step in the design tapeout process. The number of checks required and the volume of full chip design data at advanced technologies poses difficult challenges for foundries. Verification rule decks must be optimized for performance and compute memory consumption to perform the checks on the full chip with reasonable turnaround times. As verification rules can vary between technology options, as well as from one technology node to the other, a systematic method is required for abstracting the verification rules to technology-independent checks that can be easily configured and reused across multiple technologies. In this presentation, we show new methodologies that reduced the runtime of full chip ESD verification by half while maintaining all required accuracy and verification quality metrics. Samsung Foundry developed an automated flow for the generation of verification kits for different technologies so that only a configuration file is needed for each technology node to use the optimized technology-independent rules. This flow together with rule check methodologies dramatically reduces the barrier of bringing this critical tapeout step closer to the designers, ensuring the tapeout is free from any ESD issues.