Predictive design and process insights to accelerate yield ramp with Calibre fab solutions

New applications are driving the demand for new chips and semiconductor fabs need to make these chips quickly and with high yield. However, yield ramp has slowed and fabs need new ways to accelerate the path to full yield entitlement. Systematic failures that stem from process and design interactions are significant yield limiters.

Accelerate Yield Ramp with Calibre Fab Solutions

The design and process interaction is a continuous subject of research in the semiconductor world. We have come a long way from defining and enforcing well-defined rules for designs implementation and control limits for process variation to secure the IC yield; to dedicated efforts in design for manufacturing, design technology co-optimization thus responding to the increasing complexity in this interaction and the resulting failure modes. The complexity trend is continuing as we continue to shrink the feature size and increase the packing density of content. In the center of this effort is to understand the interactions and secure coverage of the design variation as well as process variation during the development phase.

The presentation provides a short review of DFM and DTCO approaches. It will show how leveraging ML techniques in the joint interpretation of layout and design analysis results, process models and process parameters and yield and reliability data can provide new insights into the complex interactions and guide the monitoring, debugging, corrective actions in both the design and process development and ramp. We will show results from using new tools in the Calibre tool suite - Calibre SONR, Calibre AIRS and Calibre DFM tools improving the quality of test chips, predicting hotspots and guiding process tuning for new product introduction.

This presentation was originally delivered at the 2021 Semicon Taiwan symposium.

About the presenter:

Dr. Steffen Schulze, Simens Digital Industries Software, VP Product Manager

Steffen Schulze is currently the Vice president of Product Management in the Calibre manufacturing group at Siemens Digital Industries Software. His group manages the product development activities for all semiconductor manufacturing software tools in the calibre product line. Steffen holds a Master's degree in Material Science from the Institute for Fine Chemical Technology M.W. Lomonosov, Moscow, Russia; a Ph.D. in Electrical Engineering from the University of Bremen, Germany; and an MBA from the University of Oregon in Eugene, Oregon USA.