Microsoft: Multi-die SSN architecture using source-synchronous timing for high-speed test delivery

Advanced multi-die package designs place significant demands on scan test data delivery, timing closure, and scalable verification. As network depth increases, conventional loop-timed SSN networks can struggle with clock skew, floorplan constraints, and I/O pad locations, placing additional limitations on the implementation.

To address this, we employ a source synchronous SSN architecture optimized for high-speed scan test in multi die designs. Our design integrates a central host die with its surrounding chiplets, forming a single package-level SSN network. SSN FIFOs and multiplexers are inserted at inter die and physical subsystem crossings to recover path delay and localize verification and timing signoff. Additionally, clocks at the output of subsystems are resynchronized to their source, thereby avoiding accumulated duty cycle distortion. This architecture simplifies SOC and package level timing signoff while also providing greater flexibility compared to loop timed SSN.