Marvell: Scalable physical verification methodology for 2.5D and 3DIC designs

Advanced 2.5D and 3D IC architectures introduce major physical verification challenges due to heterogeneous technologies, multi-foundry integration, and complex interactions across dies, substrates, and interposers. Verification scope expands further in hierarchical chiplet based designs that rely on reuse and require robust inter and intra chiplet signoff. This work presents a scalable methodology addressing these challenges through hierarchical verification flows, targeted automation, and enhanced rule checks tailored for multi-die environments. Key capabilities include advanced 3D PERC based reliability verification and automated sealring and dummy hybrid bond generation. Deployed on multiple 2.5D and 3D chiplet products, the approach improves signoff consistency, turnaround time, and design robustness, offering a practical framework for next generation semiconductor integration.