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Intel Foundry: 3D IC thermal workflow

Thermal workflow on Intel Foundry advanced packaging technologies using Innovator3D IC and Calibre 3DThermal

Estimated Watching Time: 25 minutes
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Power densities in 3D ICs are higher than in traditional SOCs due to the ability to pack more transistors into a smaller area. This trend has increased the thermal coupling between chiplets/dies, materially affecting design decisions like the floor planning, unlike in the past. Thus, having early thermal insight has become important to drive floor planning decisions during electronic designs. Moreover, as the design progresses and matures, further thermal analysis (more refined and accurate) is needed to assist design decisions. In short, a continuum of thermal modeling and simulation capability is needed starting with feasibility analysis in designing 3DICs. Intel Foundry and Siemens have come up with an integrated workflow that provides such a capability, addressing the needs of the 3DIC designs. This workflow, built on top of Siemens Innovator3D IC platform, lets an electronics designer run thermal simulations using Calibre 3DThermal from an early planning to sign off. Additionally, this workflow expedites model creation for thermal experts. In this talk, we will describe the details of this approach and present a demonstrative result using a reference design.

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