Intel: High sigma verification of large-scale libraries with a Solido AI-powered batch flow

Verifying modern standard cell libraries is challenging due to the large number of cells that need to be analyzed. Achieving accurate, full coverage high-sigma verification within production timeframes is technically difficult and extremely resource-intensive.

Solido Worst-Case Yield Solver (WCYS) is an accelerated batch flow that tackles these challenges by using AI-powered, brute-force accurate high-sigma technology that optimizes runtime and resources by dynamically generating and simulating samples only where necessary.

The Intel Standard Cell Library team has high throughput needs that require highly efficient data handling. They have collaborated with the Solido Design Environment team to increase the throughput and stability of Solido WCYS to handle >1 million simulation corners in a single batch while improving disk space, Inode, and IOPS usage to fit within practical resource limits.

Intel – Siemens collaboration improved Solido WCYS from its initial performance across several key metrics, including a 62X increase in throughput and a 46X improvement in disk space utilization. The evolution of this AI-powered approach demonstrates the capability of Solido WCYS to provide efficient and accurate verification for even the largest and most complex standard cell libraries.