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HCELL flows update

Learn about HCELL flows for Calibre LVS verification from Wael Manhawy, Calibre LVS product manager at Siemens EDA, and discover how to balance performance optimization and debuggability

Estimated Watching Time: 5 minutes

In this presentation, Wael Manhawy, Calibre LVS product manager at Siemens EDA, delves into some options for HCELL flows in Calibre LVS verification. With a focus on managing the balance between performance optimization and debuggability, Wael navigates the challenges posed by increasing device complexity, layers and connectivity statements in LVS circuit verification.

Beginning with an overview of the LVS process and the need for hierarchical netlist matching, Wael highlights the performance concerns associated with modifying layout hierarchy to enhance verification verification efficiency. He discusses the trade-offs between performance optimization and debuggability, emphasizing the need to strike a balance between the two.

Wael outlines three different HCELL flows tailored to diverse customer needs, ranging from manual approaches for expert users to automated flows for beginners. He introduces the concept of a semi-automated flow, designed to assist users in improving debuggability and runtime performance while maintaining flexibility in HCELL generation.

Finally, viewers are encouraged to download the technical paper titled: Managing the Balance Between Performance Optimization and Debuggability in LVS Verification.

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