Custom integrated circuit (IC) designers know that converging on a DRC-clean IC design is a complex and tedious job at advanced nodes (20nm and below). The DRC error fixing process can be complicated and time-consuming. Now there is a significant opportunity to reduce the time required to achieve a DRC-clean IC design. In this session, you will learn how the Calibre RealTime Custom tool in a custom design environment can accelerate DRC closure and improve designers’ productivity. The focus is on the use of the Calibre RealTime Custom tool to perform interactive signoff-quality DRC checking when fixing complex DRC errors.