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Extending design technology co-optimization from technology launch to HVM

Preventing the propagation of systematic defects in modern semiconductor design-to-fabrication process mainly relies on validation mechanism like design rule checking (DRC), optical proximity correction (OPC) verification, metrology and inspection (to gauge the process), and physical failure analysis to confirm failure diagnosis. The exchange of information and co-optimization between these steps typically happens during the early process and technology development stage via design-technology co-optimization (DTCO). Later into the process node’s lifecycle, co-optimization is facilitated by traditional techniques like design for manufacturability (DFM) and litho-friendly design (LFD). This talk presents methodologies and infrastructure necessary to feed pre-silicon design data and intelligence forward into the manufacturing process and feed manufacturing information back, post-silicon, to inform the design process.

This keynote presentation was delivered at SPIE Advanced Lithography + Patterning 2023.

Le Hong, Fan Jiang, Yuansheng Ma, Srividya Jayaram, Joe Kwan, Haizhou Yin, Xiaoyuan Qi, Junjiang Lei, “Extending design technology co-optimization from technology launch to HVM," Proceedings Volume 12495, DTCO and Computational Patterning II; 124950G (2023)

Industry trends and challenges

Most advanced fabless companies have a DFM team who use a pattern-based approach that is starting to show it's limits. These teams need new technology to help facilitate yield learning with some independence from the foundry.

The foundries meanwhile, tried using brute-force pattern-based machine learning approaches, which are costly and still not as effective as they need. They are also seeking new methodologies and tools to help cross-team collaboration with internal teams and for efficient use of all the data they generate.

The vendors of manufacturing hardware (fab equipment) and software (electronic design automation) have been working closer together and both coming up with more efficient machine learning solutions.

Challenges in going from design to final manufacturing

There are still walls between the design and manufacturing phases. The fabless company creates the design, performs DRC and DFM, then tosses it over the all to the OPC/RET team within the foundry or IDM. The design gets OPC, verification, etc., then the data are tossed over another wall to the mass manufacturing. There will be metrology and so forth to make sure everything is fine, then the printed wafer is heaved over the inspection flow, maybe followed by physical analysis. By the time a root cause of failure is found, 6-18 months have passed. That's a very long feedback loop.

Solutions for design to manufacturing

Design-technology co-optimization (DTCO) tries to break down the walls, but the methodologies available are incomplete. Traditional DTCO starts very early in the process node development. Starting with a scaling need, a standard cell is defined and we do synthesis, place, and route to come up with basic patterns and measure the performance and power. We also do SRAM yielding, do yield analysis, and use that to loop back to the standard cell design.

Our proposal is to extend this co-optimization concept to the entire process from design to manufacturing. This involves enabling the easier flow of information from design all the ay to the final process and physical analysis by creating an information channel.

In this talk, we give examples of how innovative solutions can be developed to combat some of the challenges of adopting an extended DTCO, including using a synthetic layout generator, data compression, explainable AI, and more.