Emulation Isn’t Just for ASICs

With design and communication waveforms getting larger and more complex for FPGAs, traditional simulators used to verify designs can take days to run. Because of this, a lot of tests, debug and verification of designs happen in the lab.  Lab work can take days or weeks.  Emulation is often overlooked because of the initial expenses of emulators. Here I will show that emulation can provide a productivity increase up to 620% over simulation.  Emulators run faster, provide a much larger window for signal analysis, and allow tools such as MATLAB to analyze waveforms or provide stimulus. A correlator design, used in an advanced communications system’s receiver, using nearly 1 million taps, is analyzed with both a traditional simulator, Questasim, and then run on a Veloce emulator. When contrasting the time of the 2 methods and their pros and cons, emulation might not be as cost prohibitive as originally thought.