Calibre nmLVS Recon

It is estimated that around 50% of scheduled tapeouts are delayed each year. One significant cause of these delays is the extensive time required for circuit verification. Early stage Layout Vs Schematic (LVS) verification often returns a large number of errors, some actionable and some not, that can disappear as the design progresses. Addressing connectivity issues early in the design process is crucial as they impact not only LVS but also other verification flows. As a result, designers are conducting sign-off runs on early designs, leading to thousands or even millions of errors that are resource-intensive and can be prohibitive to address.

Calibre LVS Recon, or Reconnaissance, from Siemens EDA is designed to address this challenge by fundamentally changing the LVS paradigm. It introduces a new technology that provides complete circuit verification in a "shift left" approach, enabling fast, focused, and efficient verification during early stages of design process. Similar to how cell phones revolutionized daily life over the past 40 years, Calibre LVS Recon is set to transform the way LVS is conducted, making the verification process easier and providing a shorter path to sign-off.

Before LVS Recon, designers performed sign-off runs from early design stages through to tapeout, which slows the entire design process. Now, with LVS Recon, more iterations can be performed in a single sign-off cycle, earlier, or further left, in the design flow. This results in significant savings in both machine resources and user time by focusing only on actionable errors. By adopting Calibre LVS Recon, designers can streamline their verification process, reduce errors early, and accelerate the path to tapeout. Try Calibre LVS Recon today and experience a transformative impact on your IC verification workflow.