Carey Robertson, Senior Director, Circuit Verification Tools at Siemens, discusses the Calibre Circuit Verification offerings, which include LVS and Parasitic Extraction product lines. These tools allow customers to investigate the electrical behavior of their designs. These tools are foundry-certified, from legacy nodes out to 180 nanometers, down to the most leading-edge FinFET gate-all-around technologies at three nanometer and two nanometer. With Calibre nmLVS, you can have the confidence that designers have been successfully using for IP validation through full-chip signoff. It has the capability to identify and detect your leading-edge devices, your transistors, whether they be Mosfets, FinFETs, gate-all-around transistors, as well as the other intentional devices and analog components. Our parasitic extraction tools include field solvers and inductance capabilities to offer a complete RLC interconnect model, which gives you confidence that this combined circuit model is appropriate for downstream simulation. That simulation can include Siemens Analog Fast-Spice (AFS) tools and other circuit simulators from third-party companies. It also represents the precursor to additional verification steps in Calibre PERC and our reliability verification tools.