Avoiding re-design with smart PERC adoptions - STMicroelectronics

In this session we will show two real example of Intelligent PERC use:

- The combination of Calibre PERC to check Voltage dependent rules (VDR) and SmartFill tools ensures that metal fill shapes comply with voltage and density constraints, preventing Time Dependent Dielectric Breakdown (TDDB) failures, reducing significantly the VDR verification - Tiling generation loop.

- EARLY VDROP (ST custom tool) enhances preliminary detection of current density bottlenecks at schematic level. Unlike traditional verification, EARLY VDROP operates during the schematic phase, allowing early detection and validation of potential voltage drops across all source-sink pin combinations. Three key validation stages: Schematic Topology Checks, to validate the ESD network architecture; Layout Current Density Checks to confirm compliance with ESD standards; and Schematic VDROP Checks, identifying critical low-resistance paths. The EARLY VDROP automates the exploration of ESD paths, computing voltage drops and highlighting critical low-resistance paths, reducing downstream ESD compliance failures.