The semiconductor industry's shift towards 3D stacked ICs introduces complex challenges in testing, particularly for die-to-die interconnects prone to manufacturing defects. Our approach utilizes Tessent's User Defined Fault Model (UDFM) to target these specific interconnects rather than the entire netlist to precisely model short and open interconnect defects, thereby optimizing Automatic Test Pattern Generation (ATPG) for improved test coverage and efficiency. This presentation outlines our innovative strategy in using Tessent Test Solutions to ensure the reliability of 3D stacked ICs while maintaining economic viability through reduced tester time and resource requirements for Die-to-Die interconnect test in 3D stacked ICs.