Accelerating pattern bring-up on high pin count designs

Silicon bring-up involves significant learning and is prone to errors causing increased cycle time. Arik Krantz, DFT Engineer at Broadcom, discusses accelerating pattern bring-up on high pin count designs.

Reduce time and expense of silicon bring-up

Reducing the time and expense of silicon bring-up lends a competitive
advantage to any IC company. The traditional silicon bring-up, debug, and
characterization process is prone to errors and unpredictable schedules.

This video presents a case study of the use of Tessent SiliconInsight HP on a high pin-count design from Broadcom.