Accelerating design and tape-out with Calibre

In this presentation from U2U North America 2024, Qi Wang and Paul Dorweiler​ of Marvell Semiconductor, Inc. discuss using a Calibre shift-left methodology to accelerate physical verification closure for large designs.

Addressing chip assembly and physical verification involves navigating a multi-dimensional challenge. Integrating designs with incomplete data during the early floorplan stage to detect potential issues poses a significant hurdle. Moreover, the rapid increase in merged file size not only hampers assembly efficiency but also extends physical verification run times. As a result of escalating design complexity and expansion of design rule checks, the Marvell team encounter a substantial number of violations throughout IP and chip physical verification stage. Hear how the Marvell CAD team effectively pinpointed the root causes of these issues and devised solutions through collaboration with the Siemens Calibre team. Working with the Calibre team, they were able to enhance the flow over the full design cycle with Calibre DRC Recon, Calibre LVS Recon, Calibre PERC ESD Restart and Calibre DRC split jobs. Marvell also developed in-house checks and utilities with Calibre to enhance productivity.