3D IC physical verification flow utilizing 3dblox and Calibre 3DStack demonstrated on Intel Foveros

Emerging 3D IC designs increasingly incorporate heterogeneous chiplets sourced from different foundries and technology nodes, presenting unique challenges during physical verification especially at the Layout versus Schematic (LVS) stage. Existing LVS flows demand extensive manual reconciliation of domain-specific rule decks and connectivity abstraction, resulting in scalability and integration bottlenecks. This paper introduces a fully automated LVS verification methodology tailored for 3DICs with dies from multiple foundries, leveraging the 3dblox standard for unifying die metadata, inter-die physical connectivity, and hierarchical assembly data. This session presents a comprehensive 3D integrated circuit (3D IC) physical verification methodology leveraging 3dblox and Siemens Calibre 3DSTACK, validated through Intel's Foveros Direct technology, covering Design rule checking and Layout versus Schematic Verification.