Pillar one: digitally integrated and optimized multi-domain solutions
A digitally integrated and optimized multi-domain environment enables efficient, secure, concurrent design across all engineering teams (IC, IC packaging, FPGA and PCB within electronics, as well as mechanical and software), enabling teams to optimize the costs associated with a project, accelerate design time, manage data integrity, and improve the quality of results.
Related resources
Comprehensive statistical analysis of SERDES links considering the effect of DFE error propagation
This paper proposes a statistical approach which seamlessly includes DFE into computational loop and provides required performance without simplifications.
Designing SerDes channels for protocol compliance
Multi-gigabit serial channels present some of the most stringent signal integrity challenges facing designers today. With high-speed links
Overview of SERDES channel equalization techniques for serial interfaces
In this paper, we’ll highlight some important aspects of the most popular interconnect specifications, with a focus on SERDES channel equalization techniques for Serial Interfaces.