Intel EMIB IC Package design and verification flow
With technology as complex as EMIB, the opportunity for making mistakes during the design process is increasing. Watch this presentation to learn about the Siemens design flow. In this flow we can feedback errors or concerns throughout the process and make updates to the design very quickly. By doing so we're going to reduce the high development costs and try to contain the risk of an unknown project delivery.
The Siemens solution for Intel EMIB IC packaging designs
As these systems get more complex, our ability to tightly integrate a collection of Siemens verification, design, and implementation tools allows our customers to design complex packages faster and more reliably, especially if you're if you're working with Intel.
Related resources
Calibre nmDRC Recon overview
Calibre nmDRC Recon accelerates early-stage DRC by using AI heuristics to detect systemic errors, reducing debug time and iteration cycles, ensuring faster, more efficient semiconductor design verification.
Calibre Multi-Patterning Overview
Calibre Multi-Patterning enables semiconductor designers and manufacturers to verify and optimize complex designs using advanced multi-patterning techniques, ensuring high-quality tape-outs for the most advanced process nodes.
How-to Generate Enhanced XOR rules with the DBdiff Utility
Learn how to generate enhanced XOR rules with the DBdiff utility. This provides layout-specific information for results of Layout-versus-Layout mask comparison XOR flows.