HAV VirtuaLAB accelerating SoC and IC design development - Siemens at DAC 2024

Veloce VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. Veloce VirtuaLAB significantly reduces test and compliance suite regression times, running at high emulation speeds, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario, it enables users to focus on their design's unique value while ensuring reliable standard protocol interactions.