Unsupervised ML classification driven process model coverage check

The semiconductor manufacturing’s full-chip RET/OPC operations rely on the process models calibrated against metrology data collected from custom designed test structures. Physics-based compact models and machine learning models inherently carry the issue of deficient model coverage often synonymous with calibration test pattern coverage. Therefore, process models frequently fail to predict unseen patterns within error tolerance.

With the push for advanced technology nodes, such events can even occur after a node is declared ready for high-volume manufacturing (HVM-ready). Foundries have been combating the model coverage deficiency through costly model revisions, or expensive repair flows. There has always been the desire to be able to screen and enhance compact models for potential coverage issue.

In this paper, we use a machine learning clustering platform to learn the signatures of the model calibration test patterns and then compare them to the new design patterns in terms of feature vectors’ space correlated to model parameters’ space. The comparison provides not only the locations of the new patterns but also the similarity ranking with respect to the reference pattern, so that those patterns can be included and be further analyzed for better model coverage. These patterns are often suitable candidates to be included into new model calibration sets. In this application, both the accuracy of the learning and the full-chip capability are essential. The full-chip pattern check needs to be done quickly and efficiently; hence this technology could be adopted for new chip screening, highlighting areas worth paying extra attention to during inspection.

This paper was originally presented at the 2023 SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States. It was published Proceedings Volume 12495, DTCO and Computational Patterning II; 1249518 (2023) https://doi.org/10.1117/12.2658322