The future of package design verification: Assembly design kits

Package die are often produced using multiple processes and multiple foundries, which not only raises the level of complexity, but also increases the need for a process to ensure these disparate products can be manufactured within a single package. While creating an ADK is a non-trivial effort, and requires cooperation and collaboration between design houses, assembly houses, and EDA vendors, using an ADK can reduce risk of package failure, while also reducing turnaround time for both the component providers and assembly houses.

Siemens EDA, Qualcomm, and STATS ChipPAC collaborate on assembly design kit development for 2.5/3D IC packages

Like the PDK for IC designs, an ADK provides both chip design companies and assembly houses with a standardized and validated process to ensure the manufacturability and performance of 2.5/3D IC packages. An ADK must include both a physical verification and extraction signoff solution, and it may also require thermal and/or stress signoff solutions. Engineers must be able to verify each fabric independently and at the interfacing level (die-to-die, die-to-package, etc.). All processes should be independent of any specific design tool or process used to create the assembly. In addition, a complete ADK must work across both IC and packaging domains, supporting multiple IC and package formats. Finally, all of these verification processes must be validated by the package assembly/OSAT company.

Siemens EDA collaborated with Qualcomm, an electronic design company, and STATS ChipPAC, an IC package assembly house, to develop a prototype ADK for 2.5/3D IC packages that provides a physical verification solution enabling packaging rules that are independent of any specific package design or die process. STATS ChipPAC now makes this rule file available to all customers leveraging their eWLB packaging technology to support multi-die integration.