Technical Paper

Resolution enhancement for high-NA extreme ultraviolet lithography using aperiodic multilayer masks

Metal layer type test patterns at P18 and the fixed source used to evaluate both multilayers.

In this paper, we introduce a groundbreaking approach to creating computer chips using aperiodic multilayer masks for extreme ultraviolet (EUV) lithography. The technology demonstrates exceptional performance gains, achieving a 26% improvement in vertical pattern quality and a 19% enhancement in horizontal pattern quality. Most notably, it extends the depth of focus to over 130 nm, more than doubling the 55 nm capability of conventional designs. These improvements span across various pattern types, including complex metal layer designs, making the technology highly versatile for different manufacturing needs.

The technology's effectiveness has been rigorously validated using the Siemens Calibre pxSMO software, with consistent improvements demonstrated across multiple test scenarios. This verification reinforces its practical viability in real-world manufacturing environments. This advancement positions the semiconductor industry to better meet the escalating demands for smaller, more powerful electronic devices.

This paper was presented at the 2025 SPIE Advanced Lithography + Patterning symposium and published in Optical and EUV Nanolithography XXXVIII, edited by Martin Burkhardt, Claire van Lare, Proc. of SPIE Vol. 13424, 134240D · © 2025 SPIE · 0277-786X · doi: 10.1117/12.3051972

What you'll learn:

  • How a new mask design with varying layer thicknesses improves the quality of chip manufacturing, compared to traditional periodic-layer designs
  • Why current chip-making methods struggle with smaller, advanced designs - especially when dealing with process variation and pattern accuracy
  • How the new technology was tested and validated using industry-standard tools, signaling real-world improvements of up to 26% in image quality
  • How this advancement helps create better electronic devices by improving both the precision and reliability of the manufacturing process

Who should read this:

  • Semiconductor manufacturing engineers
  • Lithography process engineers
  • Mask designers
  • Optical engineers
  • Semiconductor R&D scientists
  • Process integration engineers
  • EUV technology specialists
  • Thin film deposition engineers

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