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Pre-layout/post-layout circuit reliability verification…Do it early, do it often

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With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification to check design reliability is no longer practical for design teams. Designers must now apply reliability verification checks throughout the design flow, from intellectual property (IP) level to full-chip level, to ensure they meet tapeout schedules while confirming design reliability. This growing importance of early reliability verification drives the need for faster and easy-to use verification strategies that can be employed in earlier design stages. The Calibre PERC reliability platform packaged checks flow provides targeted pre-coded checks and a powerful user-friendly GUI that permits simple check selection and configuration, maximizing ease-of-use and minimizing runtime setup while ensuring Calibre accuracy and confidence.

Solve IC design reliability issues earlier and faster in the design flow with Calibre PERC packaged checks

To help designers meet IC design and tapeout schedules while ensuring design reliability, Calibre PERC packaged checks provide design teams with a powerful flow for early reliability verification. Using the customizable, user-friendly GUI enables designers to browse their packaged check library, easily select and configure the needed pre-coded checks based on the design criteria, and run the selected checks using the Calibre PERC reliability platform. Designers can then analyze the results using the Calibre RVE results viewer, fix any layout issues, and quickly relaunch the check(s) in an interactive flow. Together the Calibre PERC packaged checks flow and GUI enable designers to quickly and easily cover a wide range of available packaged reliability checks earlier in the design flow, reducing time to tapeout while providing Calibre confidence in the results.

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