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Technical Paper

Path-based antenna design rules reduce PID susceptibility in IC designs

Plasma-induced damage (PID) can reduce yield and reliability. Calibre PERC path-based IC design verification enables complex antenna rule checks to prevent PID in IC layouts containing multiple power domains.

Screenshot of antenna check violation in IC layout
During semiconductor manufacturing, plasma-induced damage (PID) in gate oxide (also known as the antenna effect) can negatively impact the yield and reliability of MOSFET circuits. Designers use design rule checking (DRC) in electronic design automation (EDA) flows to find and fix patterns in the integrated circuit (IC) layout design that are likely to create PID problems during manufacturing. However, a new generation of antenna design rules has emerged that cannot be checked by traditional DRC-based antenna check flows. In IC designs containing multiple power domains, some antenna checks require a path-based verification approach that understands devices, connectivity, and the formation of electrical paths within the IC design while calculating metal and MOSFET gate layer areas.

The Calibre® PERC™ reliability verification platform allows designers to identify paths of interest in IC chip designs and perform complex rule checks on those paths. This flexibility and capability enables the Calibre PERC platform to solve these emerging PID conditions. Combining the Calibre PERC path-based verification with DRC-based antenna checks provides complete coverage of both traditional and evolving antenna design rules.

Calibre PERC path-based IC design verification enables complex antenna rule checks to prevent plasma-induced damage in IC design layouts

IC designs containing multiple power domains can present cross-domain design verification challenges. Multiple isolated P-type wells in a layout means these wells cannot be effectively checked by traditional DRC-based antenna checks. While the Calibre nmDRC tool can be used to validate low-level metallization when design blocks are not fully connected, once paths across these isolated P-wells are formed, Calibre PERC path-based verification must be employed for connected IP, block/module, and full-chip signoff flows.

Taking a layout database (GDSII or OASIS format) as input, the Calibre PERC path-based antenna checking flow performs layout vs. schematic (LVS) device extraction to identify nets and devices, then follows topological paths to identify aggressor and victim devices, risk connections and protection connections, and all waiver conditions specified in foundry antenna design rules. Based on this information, the Calibre PERC platform performs area calculations and flags victim MOSFET gates with connections that do not meet area ratio requirements.

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