Optimize layout vs. layout design comparisons for faster runtimes

Layout vs. layout (LVL) comparisons provide invaluable checkpoints throughout the system-on-chip (SoC) physical design implementation methodology. Frequent LVL checks enable designers to identify and review unintended changes between the current and reference databases early in the design flow, so they can prevent the costly re-work required if these changes aren’t found until later. Optimizing LVL performance for production flows using a comparison application like the Calibre FastXOR operation ensures these comparison iterations are fast and efficient, helping to shorten design and tapeout schedules.

Optimizing layout vs. layout comparisons during SoC physical design verification ensures fast, efficient iterations and shortens design tapeout schedules

LVL data comparisons play a crucial role in identifying differences between two mask databases to validate that any differences between the two are intentional changes. Block or chip level changes made during each design iteration can introduce mask changes that could and should have been caught earlier in the design flow. As polygon counts increase throughout the SoC physical design implementation and verification flows, due to parallel chip and block-level implementations, LVL runtimes become longer. This longer runtime increases the time required for each comparison iteration and critical final tapeout stages. Optimizing LVL performance and target data comparisons not only helps reduce comparison iteration runtimes, but also ensures discrepancies are corrected as early as possible, resulting in fewer critical late-stage issues and faster overall turnaround times.