As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial runtime and resource bottlenecks. Siemens’ Calibre platform offers advanced solutions, like Calibre nmDRC Recon, that leverage a “shift-left” approach—moving verification steps earlier in the design process—to reduce debug time, manage incomplete data, and expedite the path to tape-out. This paper discusses the shift left approach and describes how a customer used Calibre nmDRC Recon to run DRC faster, with maximum check coverage and minimum compute hardware.
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