Technical Paper

The power of shift-left DRC verification with Calibre nmDRC Recon

Two panels of IC design verification visuals. The left image shows a layout overview with blue highlighting design regions, while the right image zooms in, illustrating detailed layout verification with color-coded layers and markers.

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial runtime and resource bottlenecks. Siemens’ Calibre platform offers advanced solutions, like Calibre nmDRC Recon, that leverage a “shift-left” approach—moving verification steps earlier in the design process—to reduce debug time, manage incomplete data, and expedite the path to tape-out. This paper discusses the shift left approach and describes how a customer used Calibre nmDRC Recon to run DRC faster, with maximum check coverage and minimum compute hardware.

What you’ll learn:

  • How Calibre nmDRC Recon enables early-stage, shift-left verification to reduce IC design runtimes and hardware requirements.
  • How localized checks streamline debugging and accelerate design iterations.
  • Why features like auto-waivers and split-deck runs make the DRC process more efficient.
  • How a major semiconductor company successfully reduced time-to-market and enhanced productivity using these methods.

Who should read this:

  • Engineers and designers seeking to enhance the efficiency and accuracy of their design verification process
  • CAD engineers and engineering managers looking to streamline their verification processes
  • Anyone interested in staying up to date with the latest advancements in design automation

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